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1/22 april 2002 m29f002bt, m29f002bnt m29f002bb, m29f002bnb 2 mbit (256kb x8, boot block) single supply flash memory n single 5v 10% supply voltage for program, erase and read operations n access time: 45 ns n programming time C 8 s by byte typical n 7 memory blocks C 1 boot block (top or bottom location) C 2 parameter and 4 main blocks n program/erase controller C embedded byte program algorithm C embedded multi-block/chip erase algorithm C status register polling and toggle bits n erase suspend and resume modes C read and program another block during erase suspend n unlock bypass program command C faster production/batch programming n temporary block unprotection mode n low power consumption C standby and automatic standby n 100,000 program/erase cycles per block n 20 years data retention C defectivity below 1 ppm/year n electronic signature C manufacturer code: 20h C top device code m29f002bt: b0h C top device code m29f002bnt: b0h C bottom device code m29f002bb: 34h C bottom device code m29f002bnb: 34h 32 1 tsop32 (n) 8 x 20mm plcc32 (k) pdip32 (p) figure 1. logic diagram ai02957b 18 a0-a17 w dq0-dq7 v cc m29f002bt m29f002bb m29f002bnt m29f002bnb e v ss 8 g rp
m29f002bt, m29f002bb, m29f002bnt, m29f002bnb 2/22 figure 2. plcc connections ai02959b a17 a13 a10 dq5 17 a1 a0 dq0 dq1 dq2 dq3 dq4 a7 a4 a3 a2 a6 a5 9 w a8 1 a16 a9 dq7 a12 a14 32 rp v cc m29f002bt m29f002bb m29f002bnb a15 a11 dq6 g e 25 v ss table 1. signal names a0-a17 address inputs dq0-dq7 data inputs/outputs e chip enable g output enable w write enable rp m29f002bt, m29f002bb: reset/block temporary unprotect m29f002bnt, m29f002bnb: not connected internally v cc supply voltage v ss ground figure 3. tsop connections a1 a0 dq0 a7 a4 a3 a2 a6 a5 a13 a10 a8 a9 dq7 a14 a11 g e dq5 dq1 dq2 dq3 dq4 dq6 a17 w a16 a12 rp v cc a15 ai02958 m29f002bt m29f002bb 8 1 9 16 17 24 25 32 v ss figure 4. pdip connections a1 a0 dq0 a7 a4 a3 a2 a6 a5 a13 a10 a8 a9 dq7 a14 a11 g e dq5 dq1 dq2 dq3 v ss dq4 dq6 a17 w a16 a12 rp v cc a15 ai02960 m29f002bt m29f002bb m29f002bnt 8 1 2 3 4 5 6 7 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
3/22 m29f002bt, m29f002bb, m29f002bnt, m29f002bnb summary description the m29f002b is a 2 mbit (256kb x8) non-volatile memory that can be read, erased and repro- grammed. these operations can be performed us- ing a single 5v supply. on power-up the memory defaults to its read mode where it can be read in the same way as a rom or eprom. the m29f002b is fully backward compatible with the m29f002. the memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. each block can be protected independently to prevent accidental program or erase commands from modifying the memory. program and erase commands are writ- ten to the command interface of the memory. an on-chip program/erase controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. the end table 2. absolute maximum ratings (1) note: 1. except for the rating "operating temperature range", stresses above those listed in the table "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other condition s above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating condi - tions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant qual- ity documents. 2. minimum voltage may undershoot to C2v during transition and for less than 20ns during transitions. symbol parameter value unit t a ambient operating temperature (temperature range option 1) 0 to 70 c ambient operating temperature (temperature range option 6) C40 to 85 c ambient operating temperature (temperature range option 3) C40 to 125 c t bias temperature under bias C50 to 125 c t stg storage temperature C65 to 150 c v io (2) input or output voltage C0.6 to 6 v v cc supply voltage C0.6 to 6 v v id identification voltage C0.6 to 13.5 v table 4. bottom boot block addresses, m29f002bb # size (kbytes) address range 6 64 30000h-3ffffh 5 64 20000h-2ffffh 4 64 10000h-1ffffh 3 32 08000h-0ffffh 2 8 06000h-07fffh 1 8 04000h-05fffh 0 16 00000h-03fffh of a program or erase operation can be detected and any error conditions identified. the command set required to control the memory is consistent with jedec standards. the blocks in the memory are asymmetrically ar- ranged, see tables 3a and 3b, block addresses. the first or last 64 kbytes have been divided into four additional blocks. the 16 kbyte boot block can be used for small initialization code to start the microprocessor, the two 8 kbyte parameter blocks can be used for parameter storage and the remaining 32k is a small main block where the ap- plication may be stored. chip enable, output enable and write enable sig- nals control the bus operation of the memory. they allow simple connection to most micropro- cessors, often without additional logic. the memory is offered in tsop32 (8 x 20mm), plcc32 and pdip packages and it is supplied with all the bits erased (set to 1). table 3. top boot block addresses, m29f002bt, m29f002bnt # size (kbytes) address range 6 16 3c000h-3ffffh 5 8 3a000h-3bfffh 4 8 38000h-39fffh 3 32 30000h-37fffh 2 64 20000h-2ffffh 1 64 10000h-1ffffh 0 64 00000h-0ffffh
m29f002bt, m29f002bb, m29f002bnt, m29f002bnb 4/22 signal descriptions see figure 1, logic diagram, and table 1, signal names, for a brief overview of the signals connect- ed to this device. address inputs (a0-a17). the address inputs select the cells in the memory array to access dur- ing bus read operations. during bus write opera- tions they control the commands sent to the command interface of the internal state machine. data inputs/outputs (dq0-dq7). the data in- puts/outputs output the data stored at the selected address during a bus read operation. during bus write operations they represent the commands sent to the command interface of the internal state machine. chip enable (e ). the chip enable, e , activates the memory, allowing bus read and bus write op- erations to be performed. when chip enable is high, v ih , all other pins are ignored. output enable (g ). the output enable, g , con- trols the bus read operation of the memory. write enable (w ). the write enable, w , controls the bus write operation of the memorys com- mand interface. reset/block temporary unprotect (rp ). the re- set/block temporary unprotect pin can be used to apply a hardware reset to the memory or to tem- porarily unprotect all blocks that have been pro- tected. on the m29f002bnt the pin is not connected internally and this feature is not avail- able. a hardware reset is achieved by holding reset/ block temporary unprotect low, v il , for at least t plpx . after reset/block temporary unprotect goes high, v ih , the memory will be ready for bus read and bus write operations after t phel or t plyh , whichever occurs last. see table 15 and figure 12, reset/temporary unprotect ac char- acteristics for more details. holding rp at v id will temporarily unprotect the protected blocks in the memory. program and erase operations on all blocks will be possible. the transition from v ih to v id must be slower than t phphh . reset/block temporary unprotect can be left un- connected. a weak internal pull-up resistor en- sures that the memory always operates correctly. v cc supply voltage. the v cc supply voltage supplies the power for all operations (read, pro- gram, erase etc.). the command interface is disabled when the v cc supply voltage is less than the lockout voltage, v lko . this prevents bus write operations from ac- cidentally damaging the data during power up, power down and power surges. if the program/ erase controller is programming or erasing during this time then the operation aborts and the memo- ry contents being altered will be invalid. a 0.1f capacitor should be connected between the v cc supply voltage pin and the v ss ground pin to decouple the current surges from the power supply. the pcb track widths must be sufficient to carry the currents required during program and erase operations, i cc4 . v ss ground. the v ss ground is the reference for all voltage measurements.
5/22 m29f002bt, m29f002bb, m29f002bnt, m29f002bnb table 5. bus operations note: x = v il or v ih . operation e g w address inputs data inputs/outputs bus read v il v il v ih cell address data output bus write v il v ih v il command address data input output disable x v ih v ih x hi-z standby v ih x x x hi-z read manufacturer code v il v il v ih a0 = v il , a1 = v il , a9 = v id , others v il or v ih 20h read device code v il v il v ih a0 = v ih , a1 = v il , a9 = v id , others v il or v ih b0h (m29f002bt) b0h (m29f002bnt) 34h (m29f002bb) bus operations there are five standard bus operations that control the device. these are bus read, bus write, out- put disable, standby and automatic standby. see table 5, bus operations, for a summary. typically glitches of less than 5ns on chip enable or write enable are ignored by the memory and do not af- fect bus operations. bus read. bus read operations read from the memory cells, or specific registers in the com- mand interface. a valid bus read operation in- volves setting the desired address on the address inputs, applying a low signal, v il , to chip enable and output enable and keeping write enable high, v ih . the data inputs/outputs will output the value, see figure 9, read mode ac waveforms, and table 12, read ac characteristics, for details of when the output becomes valid. bus write. bus write operations write to the command interface. a valid bus write operation begins by setting the desired address on the ad- dress inputs. the address inputs are latched by the command interface on the falling edge of chip enable or write enable, whichever occurs last. the data inputs/outputs are latched by the com- mand interface on the rising edge of chip enable or write enable, whichever occurs first. output en- able must remain high, v ih , during the whole bus write operation. see figures 10 and 11, write ac waveforms, and tables 13 and 14, write ac characteristics, for details of the timing require- ments. output disable. the data inputs/outputs are in the high impedance state when output enable is high, v ih . standby. when chip enable is high, v ih , the data inputs/outputs pins are placed in the high- impedance state and the supply current is re- duced to the standby level. when chip enable is at v ih the supply current is reduced to the ttl standby supply current, i cc2 . to further reduce the supply current to the cmos standby supply current, i cc3 , chip enable should be held within v cc 0.2v. for standby current levels see table 11, dc characteristics. during program or erase operations the memory will continue to use the program/erase supply current, i cc4 , for program or erase operations un- til the operation completes. automatic standby. if cmos levels (v cc 0.2v) are used to drive the bus and the bus is inactive for 150ns or more the memory enters automatic standby where the internal supply current is re- duced to the cmos standby supply current, i cc3 . the data inputs/outputs will still output data if a bus read operation is in progress. special bus operations additional bus operations can be performed to read the electronic signature and also to apply and remove block protection. these bus opera- tions are intended for use by programming equip- ment and are not usually used in applications. they require v id to be applied to some pins. electronic signature. the memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. these codes can be read by applying the signals listed in table 5, bus operations. block protection and blocks unprotection. each block can be separately protected against acci- dental program or erase. protected blocks can be unprotected to allow data to be changed. there are two methods available for protecting and unprotecting the blocks, one for use on pro- gramming equipment and the other for in-system use. for further information refer to application note an1122, applying protection and unprotec- tion to m29 series flash.
m29f002bt, m29f002bb, m29f002bnt, m29f002bnb 6/22 command interface all bus write operations to the memory are inter- preted by the command interface. commands consist of one or more sequential bus write oper- ations. failure to observe a valid sequence of bus write operations will result in the memory return- ing to read mode. the long command sequences are imposed to maximize data security. the commands are summarized in table 6, com- mands. refer to table 6 in conjunction with the text descriptions below. read/reset command. the read/reset com- mand returns the memory to its read mode where it behaves like a rom or eprom. it also resets the errors in the status register. either one or three bus write operations can be used to issue the read/reset command. if the read/reset command is issued during a block erase operation or following a programming or erase error then the memory will take upto 10 s to abort. during the abort period no valid data can be read from the memory. issuing a read/reset command during a block erase operation will leave invalid data in the memory. auto select command. the auto select com- mand is used to read the manufacturer code, the device code and the block protection status. three consecutive bus write operations are re- quired to issue the auto select command. once the auto select command is issued the memory remains in auto select mode until another com- mand is issued. from the auto select mode the manufacturer code can be read using a bus read operation with a0 = v il and a1 = v il . the other address bits may be set to either v il or v ih . the manufacturer code for stmicroelectronics is 20h. the device code can be read using a bus read operation with a0 = v ih and a1 = v il . the other address bits may be set to either v il or v ih . the device code for the m29f002bt is b0h, the m29f002bnt is b0h and the m29f002bb is 34h. the block protection status of each block can be read using a bus read operation with a0 = v il , a1 = v ih , and a13-a17 specifying the address of the block. the other address bits may be set to ei- ther v il or v ih . if the addressed block is protected then 01h is output on the data inputs/outputs, oth- erwise 00h is output. program command. the program command can be used to program a value to one address in the memory array at a time. the command re- quires four bus write operations, the final write op- eration latches the address and data in the internal state machine and starts the program/erase con- troller. if the address falls in a protected block then the program command is ignored, the data remains unchanged. the status register is never read and no error condition is given. during the program operation the memory will ig- nore all commands. it is not possible to issue any command to abort or pause the operation. typical program times are given in table 7. bus read op- erations during the program operation will output the status register on the data inputs/outputs. see the section on the status register for more details. after the program operation has completed the memory will return to the read mode, unless an error has occurred. when an error occurs the memory will continue to output the status regis- ter. a read/reset command must be issued to re- set the error condition and return to read mode. note that the program command cannot change a bit set at 0 back to 1. one of the erase com- mands must be used to set all the bits in a block or in the whole memory from 0 to 1. unlock bypass command. the unlock bypass command is used in conjunction with the unlock bypass program command to program the memo- ry. when the access time to the device is long (as with some eprom programmers) considerable time saving can be made by using these com- mands. three bus write operations are required to issue the unlock bypass command. once the unlock bypass command has been is- sued the memory will only accept the unlock by- pass program command and the unlock bypass reset command. the memory can be read as if in read mode. unlock bypass program command. the un- lock bypass program command can be used to program one address in memory at a time. the command requires two bus write operations, the final write operation latches the address and data in the internal state machine and starts the pro- gram/erase controller. the program operation using the unlock bypass program command behaves identically to the pro- gram operation using the program command. a protected block cannot be programmed; the oper- ation cannot be aborted and the status register is read. errors must be reset using the read/reset command, which leaves the device in unlock by- pass mode. see the program command for details on the behavior.
7/22 m29f002bt, m29f002bb, m29f002bnt, m29f002bnb table 6. commands note: x dont care, pa program address, pd program data, ba any address in the block. all values in the table are in hexadecimal. the command interface only uses address bits a0-a10 to verify the commands, the upper address bits are dont care. read/reset. after a read/reset command, read the memory as normal until another command is issued. auto select. after an auto select command, read manufacturer id, device id or block protection status. program, unlock bypass program, chip erase, block erase. after these commands read the status register until the program/erase controller completes and the memory returns to read mode. add additional blocks during block erase command with additional bus write operations until the timeout bit is set. unlock bypass. after the unlock bypass command issue unlock bypass program or unlock bypass reset commands. unlock bypass reset. after the unlock bypass reset command read the memory as normal until another command is issued. erase suspend. after the erase suspend command read non-erasing memory blocks as normal, issue auto select and program commands on non-erasing blocks as normal. erase resume. after the erase resume command the suspended erase operation resumes, read the status register until the program/ erase controller completes and the memory returns to read mode. command length bus write operations 1st 2nd 3rd 4th 5th 6th addr data addr data addr data addr data addr data addr data read/reset 1x f0 3 555 aa 2aa 55 x f0 auto select 3 555 aa 2aa 55 555 90 program 4 555 aa 2aa 55 555 a0 pa pd unlock bypass 3 555 aa 2aa 55 555 20 unlock bypass program 2x a0papd unlock bypass reset 2 x 90 x 00 chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 block erase 6+ 555 aa 2aa 55 555 80 555 aa 2aa 55 ba 30 erase suspend 1 x b0 erase resume 1 x 30 unlock bypass reset command. the unlock bypass reset command can be used to return to read/reset mode from unlock bypass mode. two bus write operations are required to issue the unlock bypass reset command. chip erase command. the chip erase com- mand can be used to erase the entire chip. six bus write operations are required to issue the chip erase command and start the program/erase controller. if any blocks are protected then these are ignored and all the other blocks are erased. if all of the blocks are protected the chip erase operation ap- pears to start but will terminate within about 100s, leaving the data unchanged. no error condition is given when protected blocks are ignored. during the erase operation the memory will ignore all commands. it is not possible to issue any com- mand to abort the operation. typical chip erase times are given in table 7. all bus read opera- tions during the chip erase operation will output the status register on the data inputs/outputs. see the section on the status register for more details. after the chip erase operation has completed the memory will return to the read mode, unless an error has occurred. when an error occurs the memory will continue to output the status regis- ter. a read/reset command must be issued to re- set the error condition and return to read mode. the chip erase command sets all of the bits in un- protected blocks of the memory to 1. all previous data is lost.
m29f002bt, m29f002bb, m29f002bnt, m29f002bnb 8/22 block erase command. the block erase com- mand can be used to erase a list of one or more blocks. six bus write operations are required to select the first block in the list. each additional block in the list can be selected by repeating the sixth bus write operation using the address of the additional block. the block erase operation starts the program/erase controller about 50s after the last bus write operation. once the program/erase controller starts it is not possible to select any more blocks. each additional block must therefore be selected within 50s of the last block. the 50s timer restarts when an additional block is selected. the status register can be read after the sixth bus write operation. see the status register for details on how to identify if the program/erase controller has started the block erase operation. if any selected blocks are protected then these are ignored and all the other selected blocks are erased. if all of the selected blocks are protected the block erase operation appears to start but will terminate within about 100s, leaving the data un- changed. no error condition is given when protect- ed blocks are ignored. during the block erase operation the memory will ignore all commands except the erase suspend and read/reset commands. typical block erase times are given in table 7. all bus read opera- tions during the block erase operation will output the status register on the data inputs/outputs. see the section on the status register for more details. after the block erase operation has completed the memory will return to the read mode, unless an error has occurred. when an error occurs the memory will continue to output the status regis- ter. a read/reset command must be issued to re- set the error condition and return to read mode. the block erase command sets all of the bits in the unprotected selected blocks to 1. all previous data in the selected blocks is lost. erase suspend command. the erase suspend command may be used to temporarily suspend a block erase operation and return the memory to read mode. the command requires one bus write operation. the program/erase controller will suspend within 15s of the erase suspend command being is- sued. once the program/erase controller has stopped the memory will be set to read mode and the erase will be suspended. if the erase suspend command is issued during the period when the memory is waiting for an additional block (before the program/erase controller starts) then the erase is suspended immediately and will start im- mediately when the erase resume command is issued. it will not be possible to select any further blocks for erasure after the erase resume. during erase suspend it is possible to read and program cells in blocks that are not being erased; both read and program operations behave as normal on these blocks. reading from blocks that are being erased will output the status register. it is also possible to enter the auto select mode: the memory will behave as in the auto select mode on all blocks until a read/reset command returns the memory to erase suspend mode. erase resume command. the erase resume command must be used to restart the program/ erase controller from erase suspend. an erase can be suspended and resumed more than once. table 7. program, erase times and program, erase endurance cycles (t a = 0 to 70c, C40 to 85c or C40 to 125c) note: 1. t a = 25 c, v cc = 5v. parameter min typ (1) typical after 100k w/e cycles (1) max unit chip erase ( all bits in the memory set to 0) 0.8 0.8 sec chip erase 2.5 2.5 10 sec block erase (64 kbytes) 0.6 0.6 4 sec program 8 8 150 s chip program 2.3 2.3 9 sec program/erase cycles (per block) 100,000 cycles
9/22 m29f002bt, m29f002bb, m29f002bnt, m29f002bnb status register bus read operations from any address always read the status register during program and erase operations. it is also read during erase sus- pend when an address within a block being erased is accessed. the bits in the status register are summarized in table 8, status register bits. data polling bit (dq7). the data polling bit can be used to identify whether the program/erase controller has successfully completed its opera- tion or if it has responded to an erase suspend. the data polling bit is output on dq7 when the status register is read. during program operations the data polling bit outputs the complement of the bit being pro- grammed to dq7. after successful completion of the program operation the memory returns to read mode and bus read operations from the ad- dress just programmed output dq7, not its com- plement. during erase operations the data polling bit out- puts 0, the complement of the erased state of dq7. after successful completion of the erase op- eration the memory returns to read mode. in erase suspend mode the data polling bit will output a 1 during a bus read operation within a block being erased. the data polling bit will change from a 0 to a 1 when the program/erase controller has suspended the erase operation. figure 5, data polling flowchart, gives an exam- ple of how to use the data polling bit. a valid ad- dress is the address being programmed or an address within the block being erased. toggle bit (dq6). the toggle bit can be used to identify whether the program/erase controller has successfully completed its operation or if it has re- sponded to an erase suspend. the toggle bit is output on dq6 when the status register is read. during program and erase operations the toggle bit changes from 0 to 1 to 0, etc., with succes- sive bus read operations at any address. after successful completion of the operation the memo- ry returns to read mode. during erase suspend mode the toggle bit will output when addressing a cell within a block being erased. the toggle bit will stop toggling when the program/erase controller has suspended the erase operation. figure 6, data toggle flowchart, gives an exam- ple of how to use the data toggle bit. error bit (dq5). the error bit can be used to identify errors detected by the program/erase controller. the error bit is set to 1 when a pro- gram, block erase or chip erase operation fails to write the correct data to the memory. if the error bit is set a read/reset command must be issued before other commands are issued. the error bit is output on dq5 when the status register is read. note that the program command cannot change a bit set at 0 back to 1 and attempting to do so may or may not set dq5 at 1. in both cases, a succes- sive bus read operation will show the bit is still 0. one of the erase commands must be used to set all the bits in a block or in the whole memory from 0 to 1. table 8. status register bits note: unspecified data bits should be ignored. operation address dq7 dq6 dq5 dq3 dq2 program any address dq7 toggle 0 CC program during erase suspend any address dq7 toggle 0 C C program error any address dq7 toggle 1 C C chip erase any address 0 toggle 0 1 toggle block erase before timeout erasing block 0 toggle 0 0 toggle non-erasing block 0 toggle 0 0 no toggle block erase erasing block 0 toggle 0 1 toggle non-erasing block 0 toggle 0 1 no toggle erase suspend erasing block 1 no toggle 0 C toggle non-erasing block data read as normal erase error good block address 0 toggle 1 1 no toggle faulty block address 0 toggle 1 1 toggle
m29f002bt, m29f002bb, m29f002bnt, m29f002bnb 10/22 figure 5. data polling flowchart read dq5 & dq7 at valid address start read dq7 at valid address fail pass ai03598 dq7 = data yes no yes no dq5 = 1 dq7 = data yes no figure 6. data toggle flowchart read dq6 start read dq6 twice fail pass ai01370b dq6 = toggle no no yes yes dq5 = 1 no yes dq6 = toggle read dq5 & dq6 erase timer bit (dq3). the erase timer bit can be used to identify the start of program/erase controller operation during a block erase com- mand. once the program/erase controller starts erasing the erase timer bit is set to 1. before the program/erase controller starts the erase timer bit is set to 0 and additional blocks to be erased may be written to the command interface. the erase timer bit is output on dq3 when the status register is read. alternative toggle bit (dq2). the alternative toggle bit can be used to monitor the program/ erase controller during erase operations. the al- ternative toggle bit is output on dq2 when the status register is read. during chip erase and block erase operations the toggle bit changes from 0 to 1 to 0, etc., with successive bus read operations from addresses within the blocks being erased. once the operation completes the memory returns to read mode. during erase suspend the alternative toggle bit changes from 0 to 1 to 0, etc. with successive bus read operations from addresses within the blocks being erased. bus read operations to ad- dresses within blocks not being erased will output the memory cell data as if in read mode. after an erase operation that causes the error bit to be set the alternative toggle bit can be used to identify which block or blocks have caused the er- ror. the alternative toggle bit changes from 0 to 1 to 0, etc. with successive bus read opera- tions from addresses within blocks that have not erased correctly. the alternative toggle bit does not change if the addressed block has erased cor- rectly.
11/22 m29f002bt, m29f002bb, m29f002bnt, m29f002bnb figure 7. ac testing input output waveform ai01275b 3v high speed 0v 1.5v 2.4v standard 0.45v 2.0v 0.8v figure 8. ac testing load circuit ai03027 1.3v out c l = 30pf or 100pf c l includes jig capacitance 3.3k w 1n914 device under test table 10. capacitance (t a = 25 c, f = 1 mhz) note: sampled only, not 100% tested. symbol parameter test condition min max unit c in input capacitance v in = 0v 6pf c out output capacitance v out = 0v 12 pf table 9. ac measurement conditions parameter m29f002b 45 / 55 70 / 90 / 120 ac test conditions high speed standard load capacitance (c l ) 30pf 100pf input rise and fall times 10ns 10ns input pulse voltages 0 to 3v 0.45 to 2.4v input and output timing ref. voltages 1.5v 0.8v and 2v
m29f002bt, m29f002bb, m29f002bnt, m29f002bnb 12/22 table 11. dc characteristics (t a = 0 to 70c, C40 to 85c or C40 to 125c) note: 1. excluding the rp input. 2. sampled only, not 100% tested. 3. t a = 25c, v cc = 5v. symbol parameter test condition min typ (3) max unit i li (1) input leakage current 0v v in v cc 1 a i lr1 rp leakage current high rp = v cc 1 a i lr2 rp leakage current low rp = v ss C0.2 C10 a i lo output leakage current 0v v out v cc 1 a i cc1 supply current (read) e = v il , g = v ih , f = 6mhz 515ma i cc2 supply current (standby) ttl e = v ih 1ma i cc3 supply current (standby) cmos e = v cc 0.2v, rp = v cc 0.2v 30 100 a i cc4 (2) supply current (program/erase) program/erase controller active 20 ma v il input low voltage C0.5 0.8 v v ih input high voltage 2 v cc +0.5 v v ol output low voltage i ol = 5.8ma 0.45 v v oh output high voltage ttl i oh = C12.5ma 2.4 v output high voltage cmos i oh = C100a v cc C0.4 v v id identification voltage 11.5 12.5 v i id identification current a9 = v id 100 a v lko (2) program/erase lockout supply voltage 3.2 4.2 v
13/22 m29f002bt, m29f002bb, m29f002bnt, m29f002bnb figure 9. read mode ac waveforms ai02961 tavav tavqv taxqx telqx tehqz tglqv tglqx tghqx valid a0-a17 g dq0-dq7 e telqv tehqx tghqz valid table 12. read ac characteristics (ta = 0 to 70c, C40 to 85c or C40 to 125c) note: 1. sampled only, not 100% tested. symbol alt parameter test condition m29f002b unit 45 55 70 / 90 / 120 t avav t rc address valid to next address valid e = v il , g = v il min 45 55 70 ns t av qv t acc address valid to output valid e = v il , g = v il max 45 55 70 ns t elqx (1) t lz chip enable low to output transition g = v il min 0 0 0 ns t elqv t ce chip enable low to output valid g = v il max 45 55 70 ns t glqx (1) t olz output enable low to output transition e = v il min 0 0 0 ns t glqv t oe output enable low to output valid e = v il max 25 30 30 ns t ehqz (1) t hz chip enable high to output hi-z g = v il max 15 18 20 ns t ghqz (1) t df output enable high to output hi-z e = v il max 15 18 20 ns t ehqx t ghqx t axqx t oh chip enable, output enable or address transition to output transition min 0 0 0 ns
m29f002bt, m29f002bb, m29f002bnt, m29f002bnb 14/22 figure 10. write ac waveforms, write enable controlled ai02083 e g w a0-a17 dq0-dq7 valid valid v cc tvchel twheh twhwl telwl tavwl twhgl twlax twhdx tavav tdvwh twlwh tghwl table 13. write ac characteristics, write enable controlled (t a = 0 to 70c, C40 to 85c or C40 to 125c) symbol alt parameter m29f002b unit 45 55 70 / 90 / 120 t avav t wc address valid to next address valid min 45 55 70 ns t elwl t cs chip enable low to write enable low min 0 0 0 ns t wlwh t wp write enable low to write enable high min 40 40 45 ns t dvwh t ds input valid to write enable high min 25 25 30 ns t whdx t dh write enable high to input transition min 0 0 0 ns t wheh t ch write enable high to chip enable high min 0 0 0 ns t whwl t wph write enable high to write enable low min 20 20 20 ns t avwl t as address valid to write enable low min 0 0 0 ns t wlax t ah write enable low to address transition min 40 40 45 ns t ghwl output enable high to write enable low min 0 0 0 ns t whgl t oeh write enable high to output enable low min 0 0 0 ns t vchel t vcs v cc high to chip enable low min 50 50 50 s
15/22 m29f002bt, m29f002bb, m29f002bnt, m29f002bnb table 14. write ac characteristics, chip enable controlled (t a = 0 to 70c, C40 to 85c or C40 to 125c) symbol alt parameter m29f002b unit 45 55 70 / 90 / 120 t avav t wc address valid to next address valid min 45 55 70 ns t wlel t ws write enable low to chip enable low min 0 0 0 ns t eleh t cp chip enable low to chip enable high min 40 40 45 ns t dveh t ds input valid to chip enable high min 25 25 30 ns t ehdx t dh chip enable high to input transition min 0 0 0 ns t ehwh t wh chip enable high to write enable high min 0 0 0 ns t ehel t cph chip enable high to chip enable low min 20 20 20 ns t avel t as address valid to chip enable low min 0 0 0 ns t elax t ah chip enable low to address transition min 40 40 45 ns t ghel output enable high chip enable low min 0 0 0 ns t ehgl t oeh chip enable high to output enable low min 0 0 0 ns t vchwl t vcs v cc high to write enable low min 50 50 50 s figure 11. write ac waveforms, chip enable controlled ai02084 e g w a0-a17 dq0-dq7 valid valid v cc tvchwl tehwh tehel twlel tavel tehgl telax tehdx tavav tdveh teleh tghel
m29f002bt, m29f002bb, m29f002bnt, m29f002bnb 16/22 table 15. reset/block temporary unprotect ac characteristics (ta = 0 to 70c, C40 to 85c or C40 to 125c) note: 1. sampled only, not 100% tested. symbol alt parameter m29f002b unit 45 55 70 / 90 / 120 t phwl (1) t phel t phgl (1) t rh rp high to write enable low, chip enable low, output enable low min 50 50 50 ns t plpx t rp rp pulse width min 500 500 500 ns t plyh (1) t ready rp low to read mode max 10 10 10 s t phphh (1) t vidr rp rise time to v id min 500 500 500 ns figure 12. reset/block temporary unprotect ac waveforms ai02943 w, rp tplpx tphwl, tphel, tphgl tplyh tphphh e, g
17/22 m29f002bt, m29f002bb, m29f002bnt, m29f002bnb table 16. ordering information scheme note: the last two characters of the ordering code may be replaced by a letter code for preprogrammed parts, otherwise devices are shipped from the factory with the memory content bits erased to 1. for a list of available options (speed, package, etc...) or for further information on any aspect of this de- vice, please contact the st sales office nearest to you. example: m29f002bb 45 n 1 t device type m29 operating voltage f = v cc = 5v 10% device function 002b = 2 mbit (256kb x8), boot block array matrix t = top boot b = bottom boot nt = top boot, no reset/block temporary unprotect pin nb = bottom boot, no reset/block temporary unprotect pin speed 45 = 45 ns 55 = 55 ns 70 = 70 ns 90 = 90 ns 120 = 120 ns package k = plcc32 n = tsop32: 8 x 20 mm p = pdip32 temperature range 1 = 0 to 70 c 6 = C40 to 85 c 3 = C40 to 125 c option t = tape & reel packing
m29f002bt, m29f002bb, m29f002bnt, m29f002bnb 18/22 table 17. revision history date rev. revision details july 1999 -01 first issue 07-oct-1999 -02 chip erase max. specification added (table 7) block erase max. specification added (table 7) program max. specification added (table 7) chip program max. specification added (table 7) i cc1 and i cc3 typ. specification added (table 11) i cc3 test condition changed (table 11) 28-jul-2000 -03 new document template document type: from preliminary data to data sheet status register bit dq5 clarification data polling flowchart diagram change (figure 5) data toggle flowchart diagram change (figure 6) 22-apr-2002 -04 m29f002bnb device added plcc32 package mechanical data modified
19/22 m29f002bt, m29f002bb, m29f002bnt, m29f002bnb plcc32 C 32 lead plastic leaded chip carrier, package outline note: drawing is not to scale. plcc32 C 32 lead plastic leaded chip carrier, package mechanical data symbol millimeters inches typ min max typ min max a 3.18 3.56 0.125 0.140 a1 1.53 2.41 0.060 0.095 a2 0.38 C 0.015 C b 0.33 0.53 0.013 0.021 b1 0.66 0.81 0.026 0.032 cp 0.10 0.004 d 12.32 12.57 0.485 0.495 d1 11.35 11.51 0.447 0.453 d2 4.78 5.66 0.188 0.223 d3 7.62 C C 0.300 C C e 14.86 15.11 0.585 0.595 e1 13.89 14.05 0.547 0.553 e2 6.05 6.93 0.238 0.273 e3 10.16 C C 0.400 C C e 1.27 C C 0.050 C C f 0.00 0.13 0.000 0.005 n32 32 r 0.89 C C 0.035 C C plcc-a d e3 e1 e 1 n d1 d3 cp b e2 e b1 a1 a r 0.51 (.020) 1.14 (.045) f a2 e2 d2 d2
m29f002bt, m29f002bb, m29f002bnt, m29f002bnb 20/22 tsop32 C 32 lead plastic thin small outline, 8 x 20mm, package outline note: drawing is not to scale. tsop32 C 32 lead plastic thin small outline, 8 x 20mm, package mechanical data symbol millimeters inches typ min max typ min max a 1.20 0.0472 a1 0.05 0.15 0.0020 0.0059 a2 0.95 1.05 0.0374 0.0413 b 0.15 0.27 0.0059 0.0106 c 0.10 0.21 0.0039 0.0083 d 19.80 20.20 0.7795 0.7953 d1 18.30 18.50 0.7205 0.7283 e 7.90 8.10 0.3110 0.3189 e 0.50 C C 0.0197 C C l 0.50 0.70 0.0197 0.0276 a 0 5 0 5 n32 32 cp 0.10 0.0039 tsop-a d1 e 1 n cp b e a2 a n/2 d die c l a1 a
21/22 m29f002bt, m29f002bb, m29f002bnt, m29f002bnb pdip32 - 32 lead plastic dip, 600 mils width, package outline note: 1. drawing is not to scale. pdip32 - 32 lead plastic dip, 600 mils width, package mechanical data symb. mm inches typ. min. max. typ. min. max. a C 5.08 C 0.2000 a1 0.38 C 0.0150 C a2 3.56 4.06 0.1402 0.1598 b 0.38 0.51 0.0150 0.0201 b1 1.52 C C 0.0598 C C c 0.20 0.30 0.0079 0.0118 d 41.78 42.04 1.6449 1.6551 d2 38.10 C C 1.5000 C C e 15.24 C C 0.6000 C C e1 13.59 13.84 0.5350 0.5449 e1 2.54 C C 0.1000 C C ea 15.24 C C 0.6000 C C eb 15.24 17.78 0.6000 0.7000 l 3.18 3.43 0.1252 0.1350 s 1.78 2.03 0.0701 0.0799 a 0 10 0 10 n32 32 pdip a2 a1 a l b1 b e1 d s e1 e n 1 c a ea eb d2
m29f002bt, m29f002bb, m29f002bnt, m29f002bnb 22/22 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners ? 2002 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - unit ed states. www.st.com

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